 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY7C1069BV33 16-Mbit (2M x 8) Static RAM Features * High speed -- tAA = 10 ns * Low active power -- 990 mW (max.) * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Available in Pb-free and non Pb-free 54-pin TSOP II package Functional Description The CY7C1069BV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE LOW) and Write Enable (WE) inputs LOW. Reading from the device is accomplished by enabling the chip (CE LOW) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW and WE LOW). The CY7C1069BV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram INPUT BUFFER Pin Configurations[1, 2] 54-pin TSOP II (Top View) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2M x 8 ARRAY I/O0-I/O7 COLUMN DECODER WE OE CE NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE VCC WE DNU/VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC DNU/VSS ROW DECODER SENSE AMPS A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 VCC NC Notes: 1. DNU/VCC Pin (#16) has to be left floating or connected to VCC and DNU/VSS Pin (#40) has to be left floating or connected to VSS to ensure proper application. 2. NC - No Connect Pins are not connected to the die. Cypress Semiconductor Corporation Document #: 38-05694 Rev. *B * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006 CY7C1069BV33 Selection Guide -10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial 10 275 275 50 -12 12 260 260 50 mA Unit ns mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[3] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage[3] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 0.3V DC Electrical Characteristics Over the Operating Range -10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Leakage Current VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs GND < VI < VCC VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Comm'l/ Ind'l Comm'l Ind'l Output Leakage Current GND < VOUT < VCC, Output Disabled Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 275 70 2.0 -0.3 -1 -1 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 260 260 70 -12 Max. Unit V V V V A A mA mA mA ISB2 50 50 mA Capacitance[4] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 6 8 Unit pF pF Thermal Resistance[4] Parameter Description Test Conditions TSOP-II 49.95 3.34 Unit C/W C/W JA JC Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring Thermal Resistance (Junction to Case) thermal impedance, per EIA/JESD51. Notes: 3. VIL (min.) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05694 Rev. *B Page 2 of 7 CY7C1069BV33 AC Test Loads and Waveforms[5] 50 OUTPUT Z0 = 50 (a) VTH = 1.5V 30 pF* *Capacitive Load consists of all components of the test environment All input pulses 3.3V GND Rise time > 1V/ns 90% 10% (c) [6] R1 317 3.3V OUTPUT *Including jig and scope 90% 10% Fall time: > 1V/ns 5 pF* R2 351 (b) AC Switching Characteristics Over the Operating Range Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Cycle[10, 11] Write Cycle Time CE to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[8] WE LOW to High-Z [8] -10 Description VCC(typical) to the First Access[7] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to CE LOW to CE to CE to Low-Z[8] Low-Z[8] 1 5 3 5 0 10 10 7 7 0 0 7 5.5 0 3 5 12 8 8 0 0 8 6 0 3 0 3 OE HIGH to High-Z[8] High-Z[8] Power-down[9] 3 10 5 1 Min. 1 10 10 3 Max. Min. 1 12 -12 Max. Unit ms ns 12 12 6 6 6 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 ns CE to Power-up[9] Notes: 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05694 Rev. *B Page 3 of 7 CY7C1069BV33 Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tASCE OE tDOE tLZOE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZSCE tPU 50% DATA VALID tPD 50% ISB ICC tHZOE tHZSCE HIGH IMPEDANCE Notes: 12. Device is continuously selected. CE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05694 Rev. *B Page 4 of 7 CY7C1069BV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW tSD DATAI/O tHD tHA Write Cycle No. 2 (WE Controlled, OE LOW)[15, 16] tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L L L OE X L X H WE X H L H I/O0-I/O7 High-Z Data Out Data In High-Z Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05694 Rev. *B Page 5 of 7 CY7C1069BV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1069BV33-10ZC CY7C1069BV33-10ZXC CY7C1069BV33-10ZI CY7C1069BV33-10ZXI CY7C1069BV33-12ZC CY7C1069BV33-12ZXC CY7C1069BV33-12ZI CY7C1069BV33-12ZXI Package Diagram 51-85160 Package Type 54-pin TSOP II 54-pin TSOP II (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) Operating Range Commercial Industrial Commercial Industrial 12 Package Diagram 54-pin TSOP II (51-85160) 51-85160-** All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05694 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1069BV33 Document History Page Document Title: CY7C1069BV33 16-Mbit (2M x 8) Static RAM Document Number: 38-05694 REV. ** *A *B ECN NO. 283950 314014 492137 Issue Date See ECN See ECN See ECN Orig. of Change RKF RKF NXR New data sheet Final data sheet Removed 8 ns speed bin Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Description of Change Document #: 38-05694 Rev. *B Page 7 of 7 |
Price & Availability of CY7C1069BV33
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |